Research Activity


Staff research engineer at Arm
Previously, post-doc electronic systems engineer at the Integrated Systems Laboratory, UPM
PhD. in Electronic Systems Engineering, Universidad Politécnica de Madrid
MSc in Electronic Systems Engineering, from the Universidad Politécnica de Madrid
5-year Engineering degree (B.S. + MSc) in Telecommunications, with a major in Electronics from the Universidad Politécnica de Madrid.
Main Research Lines
HW aware Machine Learning algorithm optimization: constraint HW and algorithms for TinyML
Computing-in-memory architectures based on memristive crossbars: HW/SW co-design
Emerging devices and Non-volatile memories modeling and simulation: MRAM, Memristor/RRAM
Intermittent Computing Systems: AMS design of system submodules, design and implementation of power and operation control unit, IC embedded software, testing platform design
IP generation and dissemination

Research Profiles

NVM Modeling & Circuit Open-Sourced Resources

  1. MRAM Simulation Framework Verilog-a compact model, Stochastic differential solver for MRAM simulation and stochastic studies.
  2. VLSI Memristor/RRAM SPICE Compact Model SPICE and Spectre model of unipolar and bipolar memristors, considering endurance and variability.
  3. Circuit Reliability Framework Reliability oriented framework for the characterization of CMOS/RRAM hybrid circuits.
  4. Memristor Application Framework Framework for the characterization and use of memristor compact models.
  5. Memristor Application Framework (Legacy) Framework for the characterization and use of memristor compact models. SMACD_2012 version.

Google Scholar Stats

AllSince 2017

Journals, International Conferences and Patents

Memory device with on-chip sacrificial memory cells
FG Redondo, M Bhargava, P Prabhat, S Jeloka
US Patent App. 17/139,059, 2022
Refactoring Mac Operations
M Mattina, S Das, GA Rosendale, FG Redondo
US Patent App. 17/674,503, 2022
Non-Volatile Memory Accelerator for Artificial Neural Networks
FG Redondo, S Das, PN Whatmough, GA Rosendale
US Patent App. 17/036,490, 2022
AnalogNets: ML-HW co-design of noise-robust TinyML models and always-on analog compute-in-memory accelerator
C Zhou, FG Redondo, J Büchel, I Boybat, XT Comas, SR Nandakumar, ...
arXiv preprint arXiv:2111.06503, 2021
Citations: 7
–17 dBm Differential charge pump EPC Gen2 UHF RFID demodulator for 9 dB receive sensitivity boost
A Savanth, P Fan, S Gamage, T Achuthan, F Garcia-Redondo
2021 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-3, 2021
A Fokker-Planck Solver to Model MTJ Stochasticity
F García-Redondo, P Prabhat, M Bhargava
ESSDERC 2021-IEEE 51st European Solid-State Device Research Conference …, 2021
A Compact Model for Scalable MTJ Simulation
F Garcia-Redondo, P Prabhat, M Bhargava, C Dray
SMACD/PRIME 2021; International Conference on SMACD and 16th Conference on …, 2021
Citations: 3
Systems and Methods of Power Management
JE Myers, P Prabhat, MJ Walker, PAK Savanth, FG Redondo
US Patent App. 16/735,606, 2021
Devices and Methods for Controlling Write Operations
FG Redondo, S Das, GA Rosendale, GMN Lattimore, M Bhargava
US Patent App. 16/582,743, 2021
Citations: 1
Refactoring MAC Computations for Reduced Programming Steps
M Mattina, S Das, GA Rosendale, FG Redondo
US Patent App. 16/556,101, 2021
Citations: 1
Non-volatile memory-based compact mixed-signal multiply-accumulate engine
S Das, M Mattina, GA Rosendale, FG Redondo
US Patent App. 16/451,205, 2020
Citations: 1
Training dnn iot applications for deployment on analog nvm crossbars
F García-Redondo, S Das, G Rosendale
2020 International Joint Conference on Neural Networks (IJCNN), 1-8, 2020
Citations: 1
27.2 M0N0: A performance-regulated 0.8-to-38MHz DVFS ARM cortex-M33 SIMD MCU with 10nW sleep power
P Prabhat, B Labbe, G Knight, A Savanth, J Svedas, MJ Walker, S Jeloka, ...
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 422-424, 2020
Citations: 10
A time-domain current-mode mac engine for analogue neural networks in flexible electronics
M Douthwaite, F García-Redondo, P Georgiou, S Das
2019 IEEE Biomedical Circuits and Systems Conference (BioCAS), 1-4, 2019
Citations: 6
Applications of computation-in-memory architectures based on memristive devices
S Hamdioui, HA Du Nguyen, M Taouil, A Sebastian, M Le Gallo, S Pande, ...
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 486-491, 2019
Citations: 25
Self-controlled multilevel writing architecture for fast training in neuromorphic RRAM applications
F García-Redondo, M López-Vallejo
Nanotechnology 29 (40), 405203, 2018
Citations: 10
Auto-erasable RRAM architecture secured against physical and firmware attacks
F García-Redondo, M López-Vallejo
IEEE Transactions on Circuits and Systems I: Regular Papers 65 (5), 1581-1590, 2017
Citations: 2
Advanced integration of variability and degradation in RRAM SPICE compact models
F García-Redondo, M López-Vallejo, CL Barrio
2017 14th International Conference on Synthesis, Modeling, Analysis and …, 2017
Citations: 7
On the design and analysis of reliable RRAM-CMOS hybrid circuits
F Garcia-Redondo, M Lopez-Vallejo
IEEE Transactions on Nanotechnology 16 (3), 514-522, 2017
Citations: 8
Resistive RAM: simulation and modeling for reliable design
F García Redondo
Telecomunicacion, 2017
Reconfigurable writing architecture for reliable RRAM operation in wide temperature ranges
F García-Redondo, P Royer, M López-Vallejo, H Aparicio, P Ituero, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (4 …, 2016
Citations: 9
Characterization of analog modules: Reliability analyses of radiation, temperature and variations effects
F García-Redondo, H Aparicio, M López-Vallejo, P Ituero, C López-Barrio
2016 Conference on Design of Circuits and Integrated Systems (DCIS), 1-5, 2016
Citations: 1
SPICE compact modeling of bipolar/unipolar memristor switching governed by electrical thresholds
F Garcia-Redondo, RP Gowers, A Crespo-Yepes, M López-Vallejo, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 63 (8), 1255-1264, 2016
Citations: 55
Taxonomy of power supply monitors and integration challenges
P Ituero, M Lopez-Vallejo, H Aparicio, F Garcia-Redondo
2016 IEEE 21st International Mixed-Signal Testing Workshop (IMSTW), 1-6, 2016
Citations: 1
Reliable design methodology: The combined effect of radiation, variability and temperature
F García-Redondo, M López-Vallejo, H Aparicio, P Ituero
2016 13th International Conference on Synthesis, Modeling, Analysis and …, 2016
Citations: 2
A thermal adaptive scheme for reliable write operation on RRAM based architectures
F Garcia-Redondo, M Lopez-Vallejo, P Ituero
2015 33rd IEEE International Conference on Computer Design (ICCD), 367-374, 2015
Citations: 4
Evolution of radiation-induced soft errors in FinFET SRAMs under process variations beyond 22nm
P Royer, F Garcia-Redondo, M Lopez-Vallejo
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale …, 2015
Citations: 15
A tool for the automatic analysis of single events effects on electronic circuits
F García-Redondo, M López-Vallejo, P Royer, J Agustín
2014 5th European Workshop on CMOS Variability (VARI), 1-6, 2014
Citations: 3
Four-injector variability modeling of FinFET predictive technology models
P Royer, M López-Vallejo, FG Redondo, CAL Barrio
2014 5th European Workshop on CMOS Variability (VARI), 1-6, 2014
Building Memristor Applications: From Device Model to Circuit Design
F Garcia-Redondo, M López-Vallejo, P Ituero
IEEE Transactions on Nanotechnology 13 (6), 1154 - 1162, 2014
Citations: 24
Improvement of Radar Capabilities by Reconfigurable Digital Signal Processing
F García-Redondo, V Iglesias, MA Sánchez, J Grajal, M López-Vallejo, ...
Conference on Design of Circuits and Integrated Systems, 2013
The tractability index of memristive circuits: branch‐oriented and tree‐based models
F García‐Redondo, R Riaza
Mathematical Methods in the Applied Sciences 35 (14), 1659-1669, 2012
Citations: 3
A CAD framework for the characterization and use of memristor models
F García-Redondo, M López-Vallejo, P Ituero, CL Barrio
2012 International Conference on Synthesis, Modeling, Analysis and …, 2012
Citations: 10
Temperature sensor placement including routing overhead and sampling inaccuracies
P Ituero, F Garcia-Redondo, M Lopez-Vallejo
2012 International Conference on Synthesis, Modeling, Analysis and …, 2012
Citations: 3
Model Validation and Simulation Framework for Novel Nanometer Devices
F García-Redondo, M López-Vallejo, P Ituero, CL Barrio
Conference on Design of Circuits and Integrated Systems (DCIS), 2012
Web-based integrated environment for self-learning electronics: the analog and digital laboratory at home
A Fernández-Herrero, P Ituero, M López-Vallejo, FG Redondo
Fourth International Conference on the Applications of Digital Information …, 2011
Citations: 1
Memory Design 10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage …
R Appeltans, P Raghavan, GS Kar, A Furnémont, L Van der Perre, ...
PhD. Thesis
Resistive RAM: Simulation and Modeling for Reliable Design
Fernando García Redondo
Advised by Marisa López-Vallejo. DOI: 10.20868/UPM.thesis.46845. Department of Electronic Engineering. Universidad Politécnica of Madrid
June. 2017
Master Thesis
Design and Implementation of a Simulation Framework for Circuits Using Memristors
Fernando García Redondo
Dept. Electronic Engineering and Department Applid Mathematics for Information Technology. Universidad Politécnica de Madrid.
Feb. 2012

CC Attribution-NonCommercial License Fernando García