Overview
Current
Principal member of technical Staff at Imec
Team Leader of Technology Enablement and Circuit Assesment Research Team
Team Leader of Technology Enablement and Circuit Assesment Research Team
Background
Staff research engineer at Arm
Post-doc electronic systems engineer at the Integrated Systems Laboratory, UPM
PhD. in Electronic Systems Engineering, Universidad Politécnica de Madrid
MSc in Electronic Systems Engineering, from the Universidad Politécnica de Madrid
5-year Engineering degree (B.S. + MSc) in Telecommunications,
with a major in Electronics from the Universidad Politécnica de Madrid.
Main Research Lines
HW aware Machine Learning algorithm optimization: constraint HW and algorithms for TinyML
Emerging devices and Non-volatile memories modeling and simulation: MRAM, Memristor/RRAM
Computing-in-memory architectures based on memristive crossbars: HW/SW co-design
Intermittent Computing Systems: AMS design of system submodules, design and implementation of power and operation control unit, IC embedded software, testing platform design
IP generation and dissemination
Research Profiles
Google Scholar
Orcid 0000-0001-7090-8821
GitHub
Research Gate
IEEEXplore
NVM Modeling & Circuit Open-Sourced Resources
Main repositories page at GitHub.
- MRAM Simulation Framework Verilog-a compact model, Stochastic differential solver for MRAM simulation and stochastic studies.
- VLSI Memristor/RRAM SPICE Compact Model SPICE and Spectre model of unipolar and bipolar memristors, considering endurance and variability.
- Circuit Reliability Framework Reliability oriented framework for the characterization of CMOS/RRAM hybrid circuits.
- Memristor Application Framework Framework for the characterization and use of memristor compact models.
- Memristor Application Framework (Legacy) Framework for the characterization and use of memristor compact models. SMACD_2012 version.
Google Scholar Stats
Journals, International Conferences and Patents
Ordered by citing relevance. Order by year
SPICE compact modeling of bipolar/unipolar memristor switching governed by electrical thresholds
F García-Redondo, RP Gowers, A Crespo-Yepes, M López-Vallejo, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 63 (8), 1255-1264, 2016
Citations: 79
2016
Applications of computation-in-memory architectures based on memristive devices
S Hamdioui, HA Du Nguyen, M Taouil, A Sebastian, M Le Gallo, S Pande, ...
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 486-491, 2019
Citations: 50
2019
27.2 M0N0: A performance-regulated 0.8-to-38MHz DVFS ARM cortex-M33 SIMD MCU with 10nW sleep power
P Prabhat, B Labbe, G Knight, A Savanth, J Svedas, MJ Walker, S Jeloka, ...
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 422-424, 2020
Citations: 29
2020
Building Memristor Applications: From Device Model to Circuit Design
F Garcia-Redondo, M López-Vallejo, P Ituero
IEEE Transactions on Nanotechnology 13 (6), 1154 - 1162, 2014
Citations: 28
2014
Ml-hw co-design of noise-robust tinyml models and always-on analog compute-in-memory edge accelerator
C Zhou, FG Redondo, J Büchel, I Boybat, XT Comas, SR Nandakumar, ...
IEEE Micro 42 (6), 76-87, 2022
Citations: 21
2022
AnalogNets: ML-HW co-design of noise-robust TinyML models and always-on analog compute-in-memory accelerator
C Zhou, FG Redondo, J Büchel, I Boybat, XT Comas, SR Nandakumar, ...
arXiv preprint arXiv:2111.06503, 2021
Citations: 21
2021
Self-controlled multilevel writing architecture for fast training in neuromorphic RRAM applications
F García-Redondo, M López-Vallejo
Nanotechnology 29 (40), 405203, 2018
Citations: 16
2018
Evolution of radiation-induced soft errors in FinFET SRAMs under process variations beyond 22nm
P Royer, F Garcia-Redondo, M Lopez-Vallejo
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale …, 2015
Citations: 15
2015
A time-domain current-mode mac engine for analogue neural networks in flexible electronics
M Douthwaite, F García-Redondo, P Georgiou, S Das
2019 IEEE Biomedical Circuits and Systems Conference (BioCAS), 1-4, 2019
Citations: 13
2019
On the design and analysis of reliable RRAM-CMOS hybrid circuits
F Garcia-Redondo, M López-Vallejo
IEEE Transactions on Nanotechnology 16 (3), 514-522, 2017
Citations: 13
2017
Reconfigurable writing architecture for reliable RRAM operation in wide temperature ranges
F García-Redondo, P Royer, M López-Vallejo, H Aparicio, P Ituero, ...
IEEE Transactions on very large scale integration (VLSI) Systems 25 (4 …, 2016
Citations: 13
2016
Ultimate MRAM scaling: Design exploration of high-density, high-performance and energy-efficient VGSOT for last level cache
M Gupta, Y Xiang, F García-Redondo, K Cai, D Abdi, HH Liu, S Rao, ...
2023 International Electron Devices Meeting (IEDM), 1-4, 2023
Citations: 10
2023
Advanced integration of variability and degradation in RRAM SPICE compact models
F García-Redondo, M López-Vallejo, CL Barrio
2017 14th International Conference on Synthesis, Modeling, Analysis and …, 2017
Citations: 10
2017
A CAD framework for the characterization and use of memristor models
F García-Redondo, M López-Vallejo, P Ituero, CL Barrio
2012 International Conference on Synthesis, Modeling, Analysis and …, 2012
Citations: 10
2012
Stt-mram stochastic and defects-aware dtco for last level cache at advanced process nodes
F García-Redondo, S Rao, M Gupta, M Perumkunnil, Y Xiang, D Abdi, ...
ESSDERC 2023-IEEE 53rd European Solid-State Device Research Conference …, 2023
Citations: 9
2023
A compact model for scalable MTJ simulation
F Garcia-Redondo, P Prabhat, M Bhargava, C Dray
SMACD/PRIME 2021; International Conference on SMACD and 16th Conference on …, 2021
Citations: 9
2021
Refactoring MAC Computations for Reduced Programming Steps
M Mattina, S Das, GA Rosendale, FG Redondo
US Patent App. 16/556,101, 2021
Citations: 7
2021
A fokker-planck solver to model mtj stochasticity
F García-Redondo, P Prabhat, M Bhargava
ESSDERC 2021-IEEE 51st European Solid-State Device Research Conference …, 2021
Citations: 6
2021
Training DNN IoT applications for deployment on analog NVM crossbars
F García-Redondo, S Das, G Rosendale
2020 International Joint Conference on Neural Networks (IJCNN), 1-8, 2020
Citations: 6
2020
Non-volatile memory accelerator for artificial neural networks
FG Redondo, S Das, PN Whatmough, GA Rosendale
US Patent 11,886,972, 2024
Citations: 4
2024
A thermal adaptive scheme for reliable write operation on RRAM based architectures
F Garcia-Redondo, M Lopez-Vallejo, P Ituero
2015 33rd IEEE International Conference on Computer Design (ICCD), 367-374, 2015
Citations: 4
2015
The tractability index of memristive circuits: branch‐oriented and tree‐based models
F García‐Redondo, R Riaza
Mathematical Methods in the Applied Sciences 35 (14), 1659-1669, 2012
Citations: 4
2012
Design space exploration of FeRAM bit cell for DRAM application
H Oh, Y Xiang, FG Redondo, MK Gupta, M Perumkunnil, MG Bardon, ...
IEEE Transactions on Electron Devices, 2024
Citations: 3
2024
Saca: System-level analog cim accelerators simulation framework: Accurate simulation of non-ideal components
GR Fernando, BG Ali, V Kanishkan, C Henk, D Shidhartha
2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS), 01-06, 2022
Citations: 3
2022
Memory for Artificial Neural Network Accelerator
TA Chou, M Bhargava, S Jeloka, FG Redondo, PN Whatmough
US Patent App. 17/242,721, 2022
Citations: 3
2022
Auto-erasable RRAM architecture secured against physical and firmware attacks
F García-Redondo, M López-Vallejo
IEEE Transactions on Circuits and Systems I: Regular Papers 65 (5), 1581-1590, 2017
Citations: 3
2017
Taxonomy of power supply monitors and integration challenges
P Ituero, M Lopez-Vallejo, H Aparicio, F Garcia-Redondo
2016 IEEE 21st International Mixed-Signal Testing Workshop (IMSTW), 1-6, 2016
Citations: 3
2016
A tool for the automatic analysis of single events effects on electronic circuits
F García-Redondo, M López-Vallejo, P Royer, J Agustín
2014 5th European Workshop on CMOS Variability (VARI), 1-6, 2014
Citations: 3
2014
Temperature sensor placement including routing overhead and sampling inaccuracies
P Ituero, F Garcia-Redondo, M Lopez-Vallejo
2012 International Conference on Synthesis, Modeling, Analysis and …, 2012
Citations: 3
2012
Resistive RAM: simulation and modeling for reliable design
FG Redondo
Universidad Politécnica de Madrid, 2017
Citations: 2
2017
Characterization of analog modules: Reliability analyses of radiation, temperature and variations effects
F García-Redondo, H Aparicio, M López-Vallejo, P Ituero, C López-Barrio
2016 Conference on Design of Circuits and Integrated Systems (DCIS), 1-5, 2016
Citations: 2
2016
Reliable design methodology: The combined effect of radiation, variability and temperature
F García-Redondo, M López-Vallejo, H Aparicio, P Ituero
2016 13th International Conference on Synthesis, Modeling, Analysis and …, 2016
Citations: 2
2016
A novel dtco-driven 1t1r bitcell for sub-10ns stt-mram llc macros at n12 node
F García-Redondo, L Verschueren, S Rao, P Pandey, D Abdi, P Weckx, ...
2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 665-668, 2024
Citations: 1
2024
Circuits and methods of detecting at least partial breakdown of canary circuits
FG Redondo, P Prabhat, M Bhargava, S Jeloka
US Patent 12,080,378, 2024
Citations: 1
2024
Stochastic Aware Modeling of Voltage Controlled Magnetic Anisotropy MRAM
B Wang, F García-Redondo, MG Bardon, H Oh, M Gupta, W Kim, ...
IEEE Transactions on Nanotechnology, 2024
Citations: 1
2024
MNEMOSENE++: Scalable multi-tile design with enhanced buffering and VGSOT-MRAM based compute-in-memory crossbar array
C Escuin, F García-Redondo, M Zahedi, P Ibáñez, T Monreal, V Viñals, ...
2023 30th IEEE International Conference on Electronics, Circuits and Systems …, 2023
Citations: 1
2023
Checkpoint-progress status
FG Redondo, J Švedas, SSHU Gamage
US Patent App. 18/316,614, 2023
Citations: 1
2023
Signalling power level threshold event to processing circuitry
SSHU Gamage, PAK Savanth, FG Redondo, J Švedas
US Patent App. 18/309,364, 2023
Citations: 1
2023
Systems and methods of power management
JE Myers, P Prabhat, MJ Walker, PAK Savanth, FG Redondo
US Patent 11,714,564, 2023
Citations: 1
2023
Saca: System-level analog cim accelerators simulation framework: Architecture and cycle-accurate system-to-device simulator
V Kanishkan, GR Fernando, BG Ali, C Henk, D Shidhartha
2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS), 01-06, 2022
Citations: 1
2022
Devices and methods for controlling write operations
FG Redondo, S Das, GA Rosendale, GMN Lattimore, M Bhargava
US Patent 11,423,985, 2022
Citations: 1
2022
Web-based integrated environment for self-learning electronics: the analog and digital laboratory at home
A Fernández-Herrero, P Ituero, M López-Vallejo, FG Redondo
Fourth International Conference on the Applications of Digital Information …, 2011
Citations: 1
2011
Magnetic Immunity of STT-MRAM: External Magnetic Field Orientation Impact on Writing Reliability
N Vander Meeren, S Van Beek, MG Monteiro, F Garcia-Redondo, ...
2024 IEEE International Electron Devices Meeting (IEDM), 1-4, 2024
2024
System Technology Co-Optimization of Cost-Bandwidth Tradeoffs in Network on Chip Through 3D Integration and Backside Signals
M Brunion, A Sharma, G Mirabelli, D Abdi, Y Zhou, H Kükner, O Zografos, ...
2024 IEEE International Electron Devices Meeting (IEDM), 1-4, 2024
2024
Ramp write techniques
S Jeloka, M Bhargava, P Prabhat, FG Redondo
US Patent 12,159,659, 2024
2024
Evaluation of a Ferroelectric Capacitor-Based Compute-in-Memory Framework
S Ray, S Mukherjee, FG Redondo, S Yu, F Catthoor, J Van Houdt, ...
2024 31st IEEE International Conference on Electronics, Circuits and Systems …, 2024
2024
Scaling NVMs in Event-Driven Architectures for Edge Inference
J Chen, K Vadivel, D Abdi, P Venugopal, R Bilgic, G Indiveri, FG Redondo, ...
2024 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 654-658, 2024
2024
Area-Efficient CFET Dual-port SRAM with Backside Interconnect
D Abdi, M Brunion, F Garcia-Redondo, P Weckx, J Boemmels, ...
2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 21-24, 2024
2024
Automatic Regression Framework for MRAM Compact Models Calibration including Stochasticity
P Graindorge, B Wang, MG Bardon, FG Redondo
2024 20th International Conference on Synthesis, Modeling, Analysis and …, 2024
2024
DTCO for Fast STT-MRAM Periphery Operation
A Hossam-Eldeen, B Wang, P Pandey, MG Bardon, FG Redondo
2024 20th International Conference on Synthesis, Modeling, Analysis and …, 2024
2024
Approximate quantile estimation
E Özer, SSHU Gamage, M Eyole, FG Redondo, J Kufel, JP Biggs
US Patent App. 18/074,636, 2024
2024
System, method and/or apparatus for magnetic memory testing
P Prabhat, M Bhargava, FG Redondo
US Patent 12,002,533, 2024
2024
A DTCO Framework for 3D NAND Flash Readout
M Gerardi, A Sharma, Y Xiang, J Kaczmarek, FG Redondo, M Rosmeulen, ...
2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-2, 2024
2024
Refactoring mac operations
M Mattina, S Das, GA Rosendale, FG Redondo
US Patent 11,922,169, 2024
2024
Non-volatile memory-based compact mixed-signal multiply-accumulate engine
S Das, M Mattina, GA Rosendale, FG Redondo
US Patent 11,886,987, 2024
2024
System, method and/device for managing memory devices
SSHU Gamage, FG Redondo, J Svedas
US Patent App. 17/814,438, 2024
2024
System-on-a-chip testing for energy harvesting devices
FG Redondo, JE Myers, PAK Savanth, P Prabhat, GD Carpenter
US Patent 11,841,397, 2023
2023
Checkpointing
FG Redondo, SSHU Gamage, J Švedas, PAK Savanth
US Patent App. 18/316,538, 2023
2023
Conductance Mapping Technique for Neural Networks
FG Redondo, M Bhargava, PN Whatmough, S Das
US Patent App. 17/689,755, 2023
2023
AR-PIM: An Adaptive-Range Processing-in-Memory Architecture
T Chou, F Garcia-Redondo, P Whatmough, Z Zhang
2023 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2023
2023
MNEMOSENE++: Scalable multi-tile design with enhanced buffering and VGSOT-MRAM based compute-in-memory crossbar array
C Escuín Blasco, F García Redondo, M Zahedi, PE Ibáñez Marín, ...
2023 30th IEEE International Conference on Electronics, Circuits and Systems …, 2023
2023
Memory device with on-chip sacrificial memory cells
FG Redondo, M Bhargava, P Prabhat, S Jeloka
US Patent 11,521,680, 2022
2022
Neural network architecture
M Eyole, S Das, FG Redondo
US Patent 11,501,150, 2022
2022
–17 dBm Differential charge pump EPC Gen2 UHF RFID demodulator for 9 dB receive sensitivity boost
A Savanth, P Fan, S Gamage, T Achuthan, F Garcia-Redondo
2021 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-3, 2021
2021
Diseño de circuitos integrados
F García Redondo
2017
Resistive RAM: simulation and modeling for reliable design
F García Redondo
Telecomunicacion, 2017
2017
Four-injector variability modeling of FinFET predictive technology models
P Royer, M López-Vallejo, FG Redondo, CAL Barrio
2014 5th European Workshop on CMOS Variability (VARI), 1-6, 2014
2014
Improvement of Radar Capabilities by Reconfigurable Digital Signal Processing
F García-Redondo, V Iglesias, MA Sánchez, J Grajal, M López-Vallejo, ...
Conference on Design of Circuits and Integrated Systems, 2013
2013
Model Validation and Simulation Framework for Novel Nanometer Devices
F García-Redondo, M López-Vallejo, P Ituero, CL Barrio
Conference on Design of Circuits and Integrated Systems (DCIS), 2012
2012
Memory Design 10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage …
R Appeltans, P Raghavan, GS Kar, A Furnémont, L Van der Perre, ...
PhD. Thesis
Resistive RAM: Simulation and Modeling for Reliable Design
Fernando García Redondo
Advised by Marisa López-Vallejo. DOI: 10.20868/UPM.thesis.46845. Department of Electronic Engineering. Universidad Politécnica of Madrid
June. 2017
Master Thesis
Design and Implementation of a Simulation Framework for Circuits Using Memristors
Fernando García Redondo
Dept. Electronic Engineering and Department Applid Mathematics for Information Technology. Universidad Politécnica de Madrid.
Feb. 2012